1. Field of the Invention
The present invention relates to a delayed signal generation circuit for generating a delayed signal.
2. Description of the Prior Art
FIG. 8 is a schematic circuit diagram showing the structure of a prior art delayed signal generation circuit. In the figure, reference numeral 1 denotes a delay element for holding an input signal during a predetermined time interval and for outputting an output signal which is delayed by the time interval with respect to the input signal, reference numeral 2 denotes an inverter which constitutes each delay element 1, and reference numeral 3 denotes a capacitor which constitutes each delay element 1.
In operation, since N delay elements 1 are connected in series in the delayed signal generation circuit of FIG. 8, when the delay time caused by each delay element 1 is T, the output signal from the final-stage delay element 1 is delayed by Nxc3x97T with respect to the input signal applied to the first-stage delay element 1.
A problem with a prior art delayed signal generation circuit constructed as mentioned above is that when a power supply voltage supplied to each delay element 1 decreases or when the operating temperature rises, the switching time of the inverter 2 which constitutes each delay element 1 increases and hence the delay time caused by each delay element 1 increases, and this results in a change in the delay time by which the output signal is delayed with respect to the input signal.
The present invention is proposed to solve the above-mentioned problem, and it is therefore an object of the present invention to provide a delayed signal generation circuit capable of generating an output signal which is delayed by a constant delay time with respect to an input signal even if the power supply voltage and/or the operating temperature changes.
In accordance with an aspect of the present invention, there is provided a delayed signal generation circuit comprising: a first delay circuit having a plurality of delay elements connected in series, the first delay circuit delaying a reference signal applied thereto; a second delay circuit having a plurality of delay elements connected in series each of which sends out an output signal which is delayed with respect to an input signal applied to the second delay circuit; a detector unit, responsive to the reference signal applied to the first delay circuit, for detecting a number of delay elements of the first delay circuit which send out an output signal that is delayed with respect to the reference signal after a lapse of a predetermined time interval; and a selection unit for selecting one delay element from among the plurality of delay elements of the second delay circuit according to the number of delay elements of the first delay circuit which is detected by the detector unit, and for sending out the output signal from the selected delay element of the second delay circuit as a delayed signal. Accordingly, the delayed signal generation circuit can generate a delayed signal that is delayed by a constant time interval with respect to the input signal even if the power supply voltage and/or the operating temperature changes.
In accordance with another aspect of the present invention, the selection unit stores correspondences between the number of delay elements of the first delay circuit which is detected by the detection unit, and one delay element of the second delay circuit which is to be selected by the selection unit. Accordingly, the delayed signal generation circuit can generate a delayed signal that is delayed by a constant time interval with respect to the input signal without complicating the structure of the delayed signal generation circuit.
In accordance with a further aspect of the present invention, the delayed signal generation circuit further comprises a unit for setting a correspondence between the number of delay elements of the first delay circuit which is detected by the detection unit, and one delay element of the second delay circuit which is to be selected by the selection unit in the selection unit and changing the correspondence stored in the selection unit based on the number of delay elements detected by the detector unit. Accordingly, the delayed signal generation circuit can generate a delayed signal that is delayed by a constant time interval with respect to the input signal even if there are variations in the manufacturing processes.
In accordance with another aspect of the present invention, the delayed signal generation circuit further comprises a unit for reducing a frequency of a clock supplied to the plurality of delay elements of the second delay circuit when the number of delay elements detected by the detector unit is less than a reference number. Accordingly, the delayed signal generation circuit can secure a low voltage margin.
In accordance with a further aspect of the present invention, the delayed signal generation circuit further comprises a unit for outputting an interruption signal that informs a decrease in a power supply voltage when the number of delay elements detected by the detector unit is less than a reference number. Accordingly, the delayed signal generation circuit can give an alarm indicating a decrease in the power supply voltage and can provide an instruction for saving of the contents of a RAM.
In accordance with another aspect of the present invention, the delayed signal generation circuit further comprises a unit for raising a power supply voltage when the number of delay elements detected by the detector unit is less than a reference number. Accordingly, the delayed signal generation circuit can keep the power supply voltage constant.
In accordance with a further aspect of the present invention, the delayed signal generation circuit further comprises a unit for controlling a power supply voltage according to the number of delay elements detected by the detection unit. Accordingly, the delayed signal generation circuit can keep the power supply voltage constant.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.